Projects · Engineering case studies

Projects

Detailed engineering breakdowns of my embedded and firmware work: architecture, technical challenges, implementation, and the engineering decisions behind each build.

01Hardware

In Progress

Custom Sensor Telemetry Board

Custom 4-layer STM32F411 PCB with FreeRTOS environmental telemetry

A custom-designed 4-layer PCB built around an STM32F411 that samples a BME280 environmental sensor over I²C and streams telemetry over USB-C, with FreeRTOS firmware coordinating acquisition and transmission.

MCU: STM32F411RET6 (LQFP-64)
Board: 4-layer · 51.2 × 40 mm
Sensor: BME280 + SSD1306 @ 400 kHz
Link: UART 921600 baud · USB-C

STM32F411FreeRTOSKiCadBME280I²CUART

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02Firmware

In Progress

Multi-Peripheral SPI Telemetry System

Bare-metal shared-bus SPI driver with a FreeRTOS telemetry pipeline on STM32F4

A bare-metal SPI driver on the STM32F446RE that services multiple peripherals on a shared bus with independent chip-select control, feeding an interrupt-driven FreeRTOS producer/consumer telemetry pipeline with fault recovery and dropped-frame detection.

MCU: STM32F446RE
Bus: SPI1 @ 1 MHz · shared, multi-CS
Model: Producer / consumer + ISR
Safety: Timeout recovery · seq. validation

STM32F446REBare-Metal CFreeRTOSSPINVICISR

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03Firmware

Completed

STM32 Bare-Metal Peripheral Driver Library

A bare-metal embedded firmware library for the STM32F4 that implements UART, I²C, and SPI by directly configuring RCC, GPIO, and peripheral registers. It includes an interrupt-driven UART receive path and a validated BMP280 sensor integration over SPI.

Core: ARM Cortex-M4 (STM32F4)
UART: 115200 baud · IRQ RX
I²C: 400 kHz Fast Mode
Sensor: BMP280 ±0.5 °C / ±1 hPa

STM32F4ARM Cortex-M4CUARTSPII²C

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04Firmware

Planned

Secure STM32 Bootloader

Planned: robust in-application firmware update with integrity checks

An upcoming bootloader project for STM32 focused on safe, recoverable firmware updates: in-application command interface, controlled bootloader entry, CRC-validated images, corrupted-image detection, and boot-loop prevention.

Status: Planned
Entry: Controlled, on next reset
Integrity: End-of-flash CRC
Safety: Boot-loop prevention

STM32BootloaderCRCFirmware UpdateReliability

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05Applied

Completed

Multi-Modal Patient Distress Detection System

Audio-triggered patient monitoring on Raspberry Pi 5 pairing FFT voice analysis with DeepFace emotion recognition

A real-time patient-monitoring system built on the Raspberry Pi 5 as part of a 5-person team. An audio stage runs FFT spectral analysis of the patient's voice and, when triggered, escalates to DeepFace facial-emotion classification through a multi-frame voting state machine, reaching roughly 1 second trigger-to-alert latency and 90% detection accuracy.

Platform: Raspberry Pi 5
Audio: FFT · 85–5000 Hz bands
Vision: DeepFace emotion
Result: 90% acc · ~1 s alert

Raspberry Pi 5PythonDeepFaceSciPy FFTOpenCVComputer Vision

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06Silicon

In Progress

Fixed-Point Streaming Attention Engine

SystemVerilog attention accelerator, verified to sky130 gate level

A tiled Q·Kᵀ matmul feeding an online softmax, written in synthesizable SystemVerilog and verified against a bit-exact dual golden model: cocotb simulation, functional coverage closure, bounded formal proofs, sky130 synthesis with OpenSTA timing, and gate-level simulation of the netlists.

Datapath: Q1.6 activations, 8-bit
Head dim: D = 16 · 1/sqrt(D) is a shift
Sequence: N ≤ 64 · N_MAX 256
Flow: Yosys → sky130 → OpenSTA

SystemVerilogRTLcocotbFormalYosysOpenSTA

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07Silicon

In Progress

UART Command Harness for an FPGA Bring-Up

8N1 UART, CDC synchronizers, and a protocol FSM in SystemVerilog

The bring-up kit that drives an attention accelerator over a serial link: an 8N1 UART receiver that votes three samples per bit, two-flop synchronizers on every asynchronous input, and a command FSM that never drops a byte. Verified end to end in cocotb against the same golden model as the core, driving only the serial pins.

Link: 8N1 UART, 115200 baud
Bit sampling: Majority of 3 per bit cell
CDC: 2-FF sync, ASYNC_REG
Target: Artix-7 XC7A35T (Basys 3)

SystemVerilogUARTCDCFSMcocotbMetastability

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Note: projects marked “In Progress” are under active development; case-study pages document the design and current implementation. Media (PCB renders, scope captures, diagrams) is being added as it is produced.

Open to opportunities

Looking for a Summer 2027 internship.

If you're hiring for embedded, firmware, or hardware roles, I'd be glad to talk through my projects and how I work. The fastest way to reach me is email.

m46saad@uwaterloo.ca Contact page

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